When designing very large scale integration ("VLSI") microchips, it is important that the power dissipation of each component be measured and accounted for so that the components are not required to operate outside of the temperature range designed for the components and the packaging utilized to encase the components. Nevertheless, many of today's VLSI chip designs, especially those implemented with CMOS FETs (complementary metal-oxide semiconductor field-effect transistors), exceed the maximum power dissipation limits allowed for many low-cost plastic packages utilized to encase the chips. The result is a resortment to higher cost packaging solutions, which of course results in higher costs passed to the end user.
Off-chip driver circuits ("OCDs") are often utilized as buffers for the input and output of signals to and from VLSI microchip logic. A large percentage of the total chip power is contributed by the OCDs. FIG. 4 illustrates conventional CMOS OCD 40 with pull-up transistor Q1 and pull-down transistor Q2 in an inverter arrangement typical of OCDs. Most of the power dissipated by an OCD is AC power, which has two primary sources. First, there is the power associated with charging and discharging the large output load capacitance C.sub.L typically coupled to the OCD. Second, if pull-up and pull-down transistors Q1 and Q2 are on simultaneously during an output transition (i.e., from high to low or from low to high), considerable power may be dissipated due to the short-circuit current from voltage source v.sub.DD to source V.sub.SS. Assuming that the short-circuit power is minimized, the majority of the AC power dissipated by OCD 40 is in charging and discharging the load capacitance C.sub.L. This power is represented by the following equation: ##EQU1## where, P.sub.AC is the AC power in milliwatts,
0.5 is the multiplier to account for a single switch in the output per clock PA1 f is the switching frequency in gigahertz, PA1 C.sub.L is the load capacitance in picofarads, PA1 V.sub.DD is the power supply voltage, and PA1 V.sub.OH is the maximum output high voltage the driver can obtain. PA1 For a conventional, full output swing OCD: P.sub.AC =0.5(.02)(75)(5).sup.2 =18.75 mW. PA1 For a reduced voltage OCD with V.sub.OH =3 volts: PA1 P.sub.AC =05(.02)(75)(5)(3)=11.25mW.
period,
As shown in the typical waveforms in FIG. 5, OCD 40 has a full output voltage swing. Therefore, the maximum output high voltage, V.sub.OH , is equal to V.sub.DD, and the above equation reduces to: EQU P.sub.AC =0.5f C.sub.L V.sub.DD.sup.2
Therefore, one solution for dissipating less power in a CMOS OCD is to reduce the output voltage swing. However, the only way to reduce the output voltage swing in conventional OCD 40 is to reduce the voltage at power supply V.sub.DD. To accomplish this feat, an additional power supply would have to be provided within the VLSI circuitry. This is not economical to do so, since CMOS circuitry typically requires a 5 volt power supply (i.e., the original voltage V.sub.DD) to operate effectively. To add a separate lower voltage power supply would increase the circuitry within the VLSI chip, and add to its corresponding cost.
The following example illustrates the reduction in AC power that may be achieved by a reduced voltage OCD which limits the output voltage swing (i.e., V.sub.OH) without requiring a separate power supply. For the purposes of this illustration, an output up-level voltage of 3.0 volts was selected as the design point for this reduced voltage OCD.
Let f=20 MHz (0.02 GHz), C.sub.L =75 pF, and V.sub.DD =5.0 volts.
As shown in this example, the reduced voltage OCD dissipates 40 percent less AC power in charging and discharging the load capacitance than the conventional OCD.
Referring next to FIG. 6, there is illustrated a prior art solution for achieving a reduced voltage OCD using an n-channel field-effect transistor ("NFET") pull-up transistor (Q1). NFET pull-ups are traditionally used in such circuits for optimizing output rising transition speed. Since the threshold voltage V.sub.THN of NFET Q1 is positive, the driven output voltage of OCD 60 is reduced to one threshold voltage drop below the gate potential. Though this characteristic is undesirable for full output swing driver circuits because the up-level is diminished, it is typically exploited in reduced voltage OCDs.
Nevertheless, OCD 60, which applies a full up-level (V.sub.DD) to the output NFET gate, does not result in optimized power reduction. The output up-level voltage of OCD 60 as compared to the full voltage swing OCD 10 of FIG. 1 is one V.sub.THN below the power supply (i.e., V.sub.OH =V.sub.DD -V.sub.THN). The effective power reduction in this instance is limited to: ##EQU2##
This is typically in the range of 10 percent, which is not near the 40 percent achieved by limiting the output voltage swing as shown above.
Therefore, what is needed is a CMOS OCD that reduces output voltage swing in order to optimize power reduction, yet provides performance characteristics comparable to full voltage swing OCD designs.